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19-2463; Rev 2; 3/03
KIT ATION EVALU BLE AVAILA
Arbitrary Graphics On-Screen Display Video Generator
General Description Features
o Generates Arbitrary Graphics Images o 15-Level Gray Scale o 8 Channels of Bit-Mapped OSD o Loss-of-Signal Detector for All Channels o Graphics Updatable Within the Vertical Interval o Update Time Stamp on All Eight Channels Simultaneously o 3V and 5V Single-Supply Operation o Works with MAX4356/MAX4358 Video Crosspoint Devices and Fast Mux Switches o Small 100-Pin TQFP Package (200mm2)
MAX4455
The MAX4455 is an eight-channel arbitrary graphics on-screen display (OSD) video generator that inserts arbitrary gray-scale bit-mapped graphics into eight asynchronous composite video sources. Ideal for security camera surveillance systems, the MAX4455 supports the insertion of graphics and text on up to eight video output channels in 15 levels of brightness. It easily displays information such as company logo, camera location, time, and date with arbitrary fonts and sizes. Arbitrary graphics capability enables the display of unique languages and fonts, allowing manufacturers to tailor their system for any geographic market. The MAX4455 is designed to work with Maxim's video crosspoint switches, such as the MAX4356 and MAX4358, which include circuitry that simplifies the insertion of the OSD information. The MAX4455 can also be used with discrete fast mux switches. The MAX4455 operates from a 3V to 3.6V digital supply, and a 2.7V to 5.5V analog supply. Independent interface supplies enable the MAX4455 to communicate with microprocessors and OSD crosspoint switch logic with logic levels ranging from 2.7V to 5.5V. The MAX4455 uses an external 16Mb SDRAM for graphical image storage for all eight video channels. The MAX4455 manages all memory interface functions, allowing a simple host P interface. The MAX4455's multiple-channel memory sharing and multiple-location write function allow fast memory updates of shared graphics information necessary for rapidly changing OSD information, such as a time stamp. The MAX4455 is available in a thin 100-pin TQFP package (200mm 2 area), and is fully specified over the extended temperature range (-40C to +85C). The MAX4455EVSYS is available to evaluate the MAX4455 along with the MAX4358 (32 x 16 video crosspoint switch with OSD).
Ordering Information
PART MAX4455ECQ TEMP RANGE -40C to +85C PIN-PACKAGE 100 TQFP
Functional Diagram
DVDD AVDD DGND AGND
MAX4455 VIDIN0 VIDEO TIMING EXTRACTION DIGITAL LINE BUFFERS 4-BIT D/A OSDFILL0
VIDIN1
VIDEO TIMING EXTRACTION
DIGITAL LINE BUFFERS
4-BIT D/A
OSDFILL1
VIDIN2
VIDEO TIMING EXTRACTION
DIGITAL LINE BUFFERS
4-BIT D/A DAC CURRENT REF
OSDFILL2
Applications
Security Systems Video Routing Industrial Applications
VIDIN7 VIDEO TIMING EXTRACTION DIGITAL LINE BUFFERS 4 BIT D/A RDY/BSY
RSET
OSDFILL7
OSDKEY0 AD7-AD0 ADDR/DATA RD WR CS 8 CPU INTERFACE MEMORY INTERFACE OSDKEY7 OSD CONTROL AND TIMING OSDKEY1 OSDKEY2
VH1
DQ RAS CAS WE BA CK
11
16
VK1
XTAL2
XTAL1/SYNC
Pin Configuration appears at end of data sheet.
MEMORY MEMORY ADDRESS DATA BUS BUS
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Arbitrary Graphics On-Screen Display Video Generator MAX4455
ABSOLUTE MAXIMUM RATINGS
AVDD to DVDD .............................................................-6V to +6V AVDD to AGND .........................................................-0.3V to +6V AVDD to DGND .........................................................-0.3V to +6V DVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V VH1, VK1 to DGND....................................................-0.3V to +6V VH1, VK1 to AGND ....................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Analog Inputs (VIDIN_) to AGND .............-0.3V to (AVDD + 0.3V) Analog Outputs (OSDFILL_) to AGND .....-0.3V to (AVDD + 0.3V) RSET to AGND .........................................-0.3V to (AVDD + 0.3V) Memory Interface to DGND .....................-0.3V to (DVDD + 0.3V) Host Interface to DGND ..............................-0.3V to (VH1 + 0.3V) OSDKEY_ to DGND.....................................-0.3V to (VK1 + 0.3V) Continuous Power Dissipation (TA = +70C) 100-Pin TQFP (derate 37.0mW/C above +70C).......2963mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD = 3.0V to 3.6V, AVDD = 2.7V to 5.5V, VK1 = VH1 = 2.7V to 5.5V, AGND = DGND = 0, RRSET = 11.75k 1%, ROSDFILL_ = 75, fXTAL1/SYNC = 40.5MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Analog Supply Voltage Digital Supply Voltage Host Supply Voltage OSDKEY Logic Supply Voltage Analog Supply Current Digital Supply Current Host Interface Static Supply Current Analog Power-Supply Rejection Ratio VIDIN_ Input Resistance OSDFILL Slew Rate White Output Voltage Accuracy Black Output Voltage OSDFILL DAC Linearity Channel-to-Channel Crosstalk Key-to-Fill Timing Delay RSET Pin Voltage OSDKEY_ Logic Output Low OSDKEY_ Logic Output High OSDKEY_ Logic Supply Current VOL VOH IVK1 VK1 = 5V, ISINK = 4mA VK1 = 5V, ISOURCE = 4mA OSDKEY_ logic levels driven to GND or VK1 2.4 10 SR FSR Output VP-P = 0.7V Pixel data = 1111 Pixel data = 0001 (Guaranteed monotonic) At 6MHz VOUT = 0.7VP-P 60 1 0.80 0.45 AVDD = 2.7V AVDD = 5.5V -8.2 -7.5 1.5 5 SYMBOL AVDD DVDD VH1 VK1 AIDD DIDD IVH1 PSRR All OSDFILL_ outputs at 100 IRE fXTAL1/SYNC = 40.5MHz Host interface logic levels driven to GND or VH1 At DC 35 100 140 +8.2 +7.5 30 10 CONDITIONS MIN 2.7 3.0 2.7 2.7 TYP MAX 5.5 3.6 5.5 5.5 190 UNITS V V V V mA mA A dB k V/s IRE IRE %FSR dB ns V V V A
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Arbitrary Graphics On-Screen Display Video Generator
P HOST INTERFACE--DC CHARACTERISTICS
(DVDD = 3.0V to 3.6V, AVDD = 2.7V to 5.5V, VK1 = VH1 = 2.7V to 5.5V, AGND = DGND = 0, RRSET = 11.75k 1%, ROSDFILL_ = 75, fXTAL1/SYNC = 40.5MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Logic Input Voltage Low Logic Input Voltage High Logic Input Current Logic Output Low Logic Output High SYMBOL VIL VIH IIL / IIH VOL VOH Sinking or sourcing VH1 = 5V, ISINK = 4mA VH1 = 5V, ISOURCE = 4mA 2.4 (0.2 x VH1) + 1.2 10 0.45 CONDITIONS MIN TYP MAX (0.2 x VH1) - 0.1 UNITS V V A V V
MAX4455
P HOST INTERFACE--AC CHARACTERISTICS
(DVDD = 3.0V to 3.6V, AVDD = 2.7V to 5.5V, VK1 = VH1 = 2.7V to 5.5V, AGND = DGND = 0, RRSET = 11.75k 1%, ROSDFILL_ = 75, fXTAL1/SYNC = 40.5MHz, CHOST = 50pF, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) (Figure 1)
PARAMETER CS, ADD/DATA, AD7-AD0 Setup Time Before WR Deassertion CS Hold After WR Deassertion Read Data Access Time Read Data Out to High-Z Time SYMBOL t1 t2 t4 t5 (Note 3) 15 CONDITIONS MIN 30 30 50 25 TYP MAX UNITS ns ns ns ns
CLOCK TIMING CHARACTERISTICS
(DVDD = 3.0 to 3.6V, AVDD = 2.7V to 5.5V, VK1 = VH1 = 2.7V to 5.5V, AGND = DGND = 0, RRSET = 11.75k 1%, ROSDFILL_ = 75, fXTAL1/SYNC = 40.5MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 4) (Figure 2)
PARAMETER Master Clock Frequency Master Clock Input Low Time Master Clock Input High Time SYMBOL fCLKIN tCLCX tCHCX CONDITIONS Crystal oscillator or externally driven for specified performance tCLKIN = 1 / fCLKIN (Note 6) tCLKIN = 1 / fCLKIN (Note 6) 10 10 MIN TYP 40.5 MAX 40.6 UNITS MHz ns ns
MEMORY INTERFACE--DC CHARACTERISTICS
(DVDD = 3.0V to 3.6V, AVDD = 2.7V to 5.5V, VK1 = VH1 = 2.7V to 5.5V, AGND = DGND = 0, RRSET = 11.75k 1%, ROSDFILL_ = 75, fXTAL1/SYNC = 40.5MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Logic Input Voltage Low Logic Input Voltage High Logic Input Current Logic Output Low Logic Output High SYMBOL VIL VIH IIL / IIH VOL VOH Sinking or sourcing DVDD = 3.3V, ISINK = 4mA DVDD = 3.3V, ISOURCE = 0.5mA 2.4 (0.2 x DVDD) + 1.3 10 0.45 CONDITIONS MIN TYP MAX (0.2 x DVDD) - 0.1 UNITS V V A V V
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
MEMORY INTERFACE TIMING CHARACTERISTICS
(DVDD = 3.0V to 3.6V, AVDD = 2.7V to 5.5V, VK1 = VH1 = 2.7V to 5.5V, AGND = DGND = 0, RRSET = 11.75k 1%, ROSDFILL_ = 75, fXTAL1/SYNC = 40.5MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Digital Output Maximum Rise Time Digital Output Maximum Fall Time Maximum Digital Out to Digital Out Skew SYMBOL tCLCH tCHCL tSKEW CONDITIONS 15pF load (Note 5) 15pF load (Note 5) 15pF load, except D0-D15 MIN TYP 3 3 2.5 MAX UNITS ns ns ns
Note 1: fXTAL1/SYNC is production tested at 1MHz. Application operating frequency is fXTAL1/SYNC = 40.5MHz. Note 2: Pertains to host interface pins: ADDR/DATA, CS, WR, RD, AD7-AD0, RDY/BSY. VH1 is connected to P host power supply rail (2.7V to 5.5V). Note 3: Read operation is combinational. Access time is from the latter of either RD or CS. Note 4: Pertains to XTAL1/SYNCIN and XTAL2 pins (external clock is supplied to XTAL1/SYNCIN pin). All input signals are specified with tR = tF = 5ns (10% to 90% of DVDD), and timed from a voltage level of 1.6V. Note 5: Specified using 10% and 90% points.
Timing Diagrams
t1 t2 CS ADD/DATA XTAL1/SYNC VIL VIH ADDR/DATA IN tCHCX
AD7-AD0 WR
HOST ADDRESS OR DATA WRITE OPERATION
tCLCX
ADD/DATA t3
tCLCH
VIH CS AD7-AD0 t4 RD READ DATA OUT t5 tCHCL MEMORY LOGIC I/O VIL
HOST DATA READ OPERATION
Figure 1. P Host Interface Timing
Figure 2. Clock and Memory Timing Diagram
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Arbitrary Graphics On-Screen Display Video Generator
Typical Operating Characteristics
(AVDD = 5V, DVDD = 3.3V, RRSET = 11.75k, TA = +25C, unless otherwise noted.)
FULL-SCALE OUTPUT vs. RRSET
MAX4455 toc01
MAX4455
DAC OUTPUT vs. DAC CODE
MAX4455 toc02
DAC OUTPUT vs. DAC CODE vs. RRSET
200 175 DAC OUTPUT (IRE) 150 125 100 75 50 25 0 RRSET = 14.598k RRSET = 17.516k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DAC CODE RRSET = 11.75k RRSET = 7.636k
MAX4455 toc03
225 200 FULL-SCALE OUTPUT (IRE) 175 150 125 100 75 50 25 0 4 5 6 7 8
110 100 90 DAC OUTPUT (IRE) 80 70 60 50 40 30 20 10 0
RRSET = 11.75k
225 RRSET = 5.716k
9 10 11 12 13 14 15 RRSET (k)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DAC CODE
VIDEO LINE OUTPUT WITH OSD
MAX4455 toc04
VIDEO LINE OUTPUT WITH OSD (EXPANDED TIME SCALE)
MAX4455 toc05
0 A A 0
B
0
B
0
C D
0
C
0
0 10s/div A: VCAMERA (NTSC COMPOSITE), 500mV/div B: VCAMERA + OSDFILL, 500mV/div C: VOSDFILL, 500mV/div D: VOSDKEY, 5V/div NOTE: MEASUREMENT MADE WITH MAX4455EVSYS.
D 1s/div
0
A: VCAMERA (NTSC COMPOSITE), 500mV/div B: VCAMERA + OSDFILL, 500mV/div C: VOSDFILL, 500mV/div D: VOSDKEY, 5V/div NOTE: MEASUREMENT MADE WITH MAX4455EVSYS.
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Typical Operating Characteristics (continued)
(AVDD = 5V, DVDD = 3.3V, RRSET = 11.75k, TA = +25C, unless otherwise noted.)
Figure 3. On-Screen Display Capability of the MAX4455
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Arbitrary Graphics On-Screen Display Video Generator
Pin Description
PIN 2, 1, 100, 99, 98, 97, 96, 95 3 4, 25, 33, 42, 50, 58, 66, 72, 75 5 6 7 8 9-16 17 18-23, 26, 27, 37, 36, 35, 34, 31, 30, 29, 28 24, 32, 41, 49, 57, 71 38 39 48 51 52 53 55, 56, 59, 60, 47, 46, 45, 44, 43, 40, 54 61-64, 67-70 NAME VIDIN0-VIDIN7 VH1 DGND CS WR RD ADDR/DATA AD7-AD0 RDY/BSY D0-D15 DVDD DQM CLK WE CAS RAS BA A0-A10 OSDKEY0- OSDKEY7 FUNCTION Analog Video Inputs. The MAX4455 extracts video timing information from each VIDIN_ input. AC-couple the input signal with a 0.1F capacitor. Host Interface Supply Voltage Input. VH1 supplies the level shifters for logic outputs to the host P interface. Connect VH1 to the P logic supply. Digital Ground Host Chip Select Digital Input. Drive CS logic high to enable the host data interface. Host Write Strobe Digital Input Host Read Strobe Digital Input Host Address or Data Select Digital Input Host Address/Data Bus Digital I/O Host Ready/Busy Handshake Digital Output Memory Data Digital I/O Positive Digital Power Supply. Bypass each DVDD pin with a 0.1F capacitor to DGND. Memory DQM Digital Output. DQM controls the memory output buffer in read mode, and masks input data in write mode. Memory Clock Digital Output Memory Write Enable Digital Output Memory Column Address Strobe Digital Output Memory Row Address Strobe Digital Output Memory Bank Address Digital Output Memory Address Digital Outputs OSDKEY Digital Outputs. OSDKEY_ logic low controls the fast mux switches (available in the Maxim crosspoint switches, MAX4356/MAX4358) to insert OSDFILL_ signal. OSDKEY Interface Power-Supply Input. VK1 supplies the level shifters for OSDKEY_ logic outputs to the fast mux switches (available in the Maxim crosspoint switches, MAX4356/MAX4358). Connect VK1 to the digital supply of the fast mux switches (VDD of the MAX4356/MAX4358). Crystal Oscillator/External Clock Input. Connect a crystal oscillator module to XTAL1/SYNC, or connect a fundamental mode crystal oscillator between XTAL1/SYNC and XTAL2. Crystal Oscillator Output. Leave XTAL2 unconnected when using a crystal oscillator module, or connect a fundamental mode crystal oscillator between XTAL1/SYNC and XTAL2. Positive Analog Power Supply. Bypass each AVDD pin with a 0.1F capacitor to AGND. OSDFILL Analog Outputs. OSDFILL_ are video DAC current outputs and require a termination resistor (nominally 75) to AGND.
MAX4455
65
VK1
73
XTAL1/SYNC
74 76, 78, 80, 82, 84, 86, 88, 90, 92 77, 79, 81, 83, 85, 87, 89, 91
XTAL2
AVDD OSDFILL7- OSDFILL0
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Pin Description (continued)
PIN 93 94 NAME RSET AGND FUNCTION OSDFILL Reference Voltage. Connect a resistor (typically 11.75k) from RSET to AGND to set the full-scale output current of all eight OSDFILL_ outputs. Analog Ground
Detailed Description
The MAX4455 provides 4-bit gray-scale graphics video to eight simultaneous independent composite video inputs. The bit-mapped approach allows an arbitrary message to be inserted into the camera video when used in conjunction with the MAX4356/MAX4358 video crosspoint switch or discrete fast mux switch. The inserted graphics can include camera location, date, time, company logo, or warning prompts. The graphics palette for each of the eight video channels in the MAX4455 is logically organized into 1024 pixels by 512 lines. This memory arrangement facilitates easy row/column pixel addressing by the host processor. The actual displayed area is 712 x 484 NTSC (712 x 512 PAL) pixels. The remaining 312 logical pixels per line are blanked. The remaining 28 NTSC (0 PAL) horizontal lines are also blanked as shown in Figure 4. The MAX4455 controls a 16Mb SDRAM (such as MT48LC1M16A) that stores video graphics insertion data. The MAX4455 performs all SDRAM support functions, including refresh, RAS/CAS timing, video addressing, and CPU access cycles for host processor read/write support. Since the SDRAM is organized as a 16-bit wide x 1 million deep array, each SDRAM memory location holds 4 pixels (based on the fact that a pixel is 4 bits and memory is 16 bits wide). The host processor thus accesses pixels four at a time. The host processor interface is 8 bits wide so the 16 bit wide SDRAM data is written into (or read from) the pixel data register as two separate 8-bit bytes. The MAX4455 establishes a video raster time base by sensing the video signal on either the output of the Maxim crosspoint switch, or the output buffer of the fast mux switch. The MAX4455 uses this raster timing to produce an OSD image signal that can be inserted into the camera video by controlling the OSDKEY input to the Maxim crosspoint switch or fast mux switch. The OSD image is inserted wherever the OSD video level pixel code has a nonzero value, and the crosspoint switch or discrete fast mux is made to pass the original video wherever the OSD video level pixel code is zero. When the OSD video level is nonzero, it represents a gray-level code such that level 1 is near black and code 15 (the maximum possible with a 4-bits-per-pixel
8
code) is maximally white (Table 1). The host computer fills the external OSD frame memory with a bit-mapped image such that each pixel has a value between zero and 15, controlling both insertion locations and the brightness levels within an inserted video image. There are eight channels in the MAX4455 that share memory resources but are logically completely independent. Writing/reading image data to/from any channel's memory does not disrupt other channels. The MAX4455 features a memory-sharing function where the even channels or the odd channels can be updated simultaneously by writing to a designated source channel. The memory-sharing function minimizes the number of memory writes by the host processor. This is useful for updating information that changes rapidly (i.e., time stamp).
Video Inputs
The MAX4455's eight VIDIN_ inputs include circuitry to extract video timing from each asynchronous video channel for proper display of the OSD specific to that channel. Each VIDIN_ time-base circuitry includes a horizontal sync detector, vertical sync detector, vertical interval detector, horizontal line counter, and even/odd field counter. The VIDIN_ inputs sense a standard 1VP-P video signal at the output of the crosspoint switch, or fast mux buffer in order to make video timing insensitive to delays through the switch/mux. AC-couple the input with a 0.1F capacitor.
OSDFILL_ Video Outputs
The MAX4455 has eight independent current output video DACs that provide 7 IRE to 100 IRE video levels (R RSET = 11.75k) when terminated with 75 to AGND. Connect OSDFILL_ to either the OSDFILL_ input of the Maxim crosspoint switch (MAX4356/ MAX4358) or to one of the inputs of the fast mux switch.
OSDKEY Control Outputs
Each OSD channel has an OSDKEY_ logic output that drives low when OSDFILL_ output video is to be multiplexed into the active video. The OSDKEY_ output interfaces directly to the OSDKEY_ inputs of the MAX4356/MAX4358 or control inputs of the fast mux switch to allow pixel-by-pixel OSD insertion. The VK1 supply sets the OSDKEY_ logic output voltage levels.
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Arbitrary Graphics On-Screen Display Video Generator
Table 1. Pixel Data Mapping (4 Bits per Pixel)
PIXEL DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 GRAY SCALE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESCRIPTION Transparent--no OSD insertion. Background video appears normally. 7 IRE (black) 13 IRE 20 IRE 27 IRE 33 IRE 40 IRE 47 IRE 53 IRE 60 IRE 67 IRE 73 IRE 80 IRE 87 IRE 93 IRE 100 IRE (white)
Microprocessor Interface
The MAX4455 P interface includes a byte-wide address/data bus (AD7-AD0) for parallel programming of the MAX4455, write strobe input (WR), read strobe input (RD), active-high chip-select input (CS), address or data-select input (ADDR/DATA), and a ready/busy hand-shaking output (RDY/BSY) (Figures 5 and 6). The MAX4455 allows for interfacing to a P powered from a different supply than the MAX4455 by connecting VH1 to the P supply. For example, the MAX4455 can be operated with a single 3.3V supply, while the P interface can be operated with 3.3V or 5V logic levels by connecting VH1 to the P power supply.
MAX4455
Host Access Protocol Sequence
1) Host sets ADD/DATA = 1. 2) Host outputs register address on AD7-AD0. 3) Host pulses WR low, then high to write register address. 4) Host checks RDY/BSY = 1 (host waits if RDY/BSY = 0). For register data writes: 1) Host sets ADD/DATA = 0. 2) Host drives register data on AD7-AD0. 3) Host pulses WR low, then high. For register data reads: 1) Host removes drive from AD7-AD0 in anticipation of register read operation and sets ADD/DATA = 0. 2) Host then pulses RD low and reads register data. 3) The MAX4455 three states when RD is deasserted (high).
Connect VK1 to the MAX4356/MAX4358 VDD logic supply, or a 5V logic supply for TTL output compatibility.
OSDFILL_ Reference Voltage (RSET)
Set the video DAC's full-scale output current for all eight channels by connecting a resistor between RSET and ground. The nominal 11.75k RRSET provides a 100 IRE video output level when OSDFILL_ outputs are terminated with 75 resistors to ground. RRSET can typically range between 5k and 15k. The full-scale OSD DAC output current = (106.5) / RRSET. The full-scale OSD DAC output voltage is the OSD DAC output current x ROSDFILL, where ROSDFILL_ is the termination resistor to AGND at OSDFILL_.
SDRAM Memory Interface
The MAX4455 interfaces directly to a 16Mb SDRAM with 16-bit-wide data bus. The MAX4455 performs all SDRAM support functions, including refresh, RAS/CAS timing, data addressing, and CPU access cycles for host processor read/write support.
MAX4455 Register Description
OSD Register Organization
The host processor controls each of the MAX4455's eight video channels through eight groups (blocks) of 8bit command, status, data, and address registers, plus one multichannel register block. The register set description for a single channel is described in Table 2. The eight identical sets of 16 registers (14, plus 2 reserved) are selected by 4 LSB bits in the host interface address field as described in Tables 3 and 4. The lower address bits select which register is accessed within any given channel. Even channels can share buffer data for display
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Crystal Oscillator
The MAX4455 requires a 40.5MHz clock. Connect a 3.3V crystal oscillator module to XTAL1/SYNC and leave XTAL2 unconnected, or connect a lower cost 40.5MHz fundamental mode crystal between XTAL1/SYNC and XTAL2. The MAX4455 is designed to operate with a 50% clock duty cycle, but typically operates with up to 40% to 60% duty cycles. The oscillator circuitry typically requires 10ms to settle after the DVDD supply is powered up.
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
tFRAME = 33.367ms T = 1 / (13.5MHz) = 74.074ns = 1 PIXEL TIME VERTICAL 1 (20 NTSC LINES, 25 PAL LINES)
FLD1: 262H/ 312H (PAL)
HBLANK
FIELD 1 ACTIVE VIDEO (242H NTSC, 287H PAL)
525H / 625H PER FRAME
VERTICAL 2 (21 NTSC LINES, 26 PAL LINES)
FLD2: 263H/ 313H (PAL)
HBLANK
FIELD 2 ACTIVE VIDEO (242H NTSC, 287 PAL)
APPROX 144T NTSC, 162T PAL HBLANK PIXEL COUNT IS DEPENDENT UPON INCOMING VIDEO HLINE PERIOD
712T NTSC, 702T PAL 1ST DISPLAYED PIXEL POSITION IS CONTROLLED BY HOFFSET REGISTER
Figure 4. OSD Raster Dimensions
among even channels. Odd channels can also share buffer data for display among odd channels (see the Memory Sharing section).
P DIGITAL SUPPLY 2.7V TO 5.5V
MAX4455 DIGITAL SUPPLY 3V TO 3.6V
Detailed Description of the Channel-N Block Registers
QPH, QPL (Quad Pixel Register) Read/write pixel data 16-bits at a time to the quad pixel registers due to the SDRAM memory organization. The 4 MSBs (nybble) of QPH represent the left-most pixel and the 4 LSBs of QPL represent the right-most pixel (4 bits per pixel). To transfer the QPH/QPL value into display memory, set the QPHORIZ/QPLINE registers and then write 0000 0010 to the command register (see Command Register section). QPHORIZ This 8-bit value is the address of the quad pixel within the line specified by QPLINE HI and QPLINE LO. A zero in QPHORIZ addresses the leftmost displayed quad pixel in the specified line, and increasing QPHORIZ addresses indexes towards the right-hand side of the video screen. Valid values range from zero to 177. Write a 1 in the HINC bit of the channel status register to enable autoincrement of QPHORIZ. QPHORIZ autoincrement saturates at 177.
VCC
VH1 WR RD
DVDD
P DATA BUS GPIO 8
ADD/DATA AD7-AD0 RDY/BSY CS
P HOST INTERFACE
MAX4455
Figure 5. P Host Interface
QPLINEH, QPLINEL The QPLINE_ 9-bit address specifies the horizontal line of the quad pixel to be accessed (host read or write). The 9th bit resides in the LSB position (bit 0) of the QPLINEH register. The lower 8 bits of the 9-bit address are specified by QPLINEL. Table 5 shows valid displayed line numbers. Note that for NTSC, lines 1 through 20 are never valid, as this is the vertical blank interval. Write a 1 in the VINC bit of the channel status register to enable autoincrement of QPLINE_. QPLINE_ autoincrement saturates at 511.
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Arbitrary Graphics On-Screen Display Video Generator
STATUS The channel status register contains a group of individual control bits and a loss-of-sync (LOS) flag bit. BLANK (when set to 1) forces suppression of the OSD insertion graphics, independent of the memory contents. ASYNC (when set to 1) enables the SHRxxxx registers to be updated by the host immediately; otherwise, they are updated at the next complete video field. HINC (when set to 1) enables autoincrement of the QPHORIZ regisThe channel status register is described below:
BIT7 0 0 0 VINC HINC ASYNC BLANK BIT0 LOS
ter after each host read/write to OSD memory. VINC (when set to 1) enables autoincrement of QPLINEH/L after each host read/write to OSD memory. The LOS flag is useful in detecting the presence (or absence) of composite video at the channel VIDIN_. LOS is a 1 if the channel's valid composite sync is lost for more than one horizontal line period. It resets back to zero once a valid sync pulse is detected.
MAX4455
CS ADD/DATA HIGH-Z
AD7-AD0 WR
ADDRESS
DATA IN
RD
HOST ADDRESS AND DATA WRITE OPERATION
CS ADD/DATA
AD7-AD0 WR RD
HIGH-Z
ADDRESS
DATA OUT
HOST ADDRESS AND DATA READ OPERATION
Figure 6. Host Data Write and Read Sequences
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Table 2. Channel-N Block Register Map
ADDRESS 0nnn0000 0nnn0001 0nnn0010 0nnn0011 0nnn0100 0nnn0101 0nnn0110 0nnn0111 0nnn1000 0nnn1001 0nnn1010 0nnn1011 0nnn1100 0nnn1101 0nnn1110 0nnn1111 NAME QPH QPL QPHORIZ QPLINEH QPLINEL STATUS COMMAND HOFFSET VOFFSET SHRSRC SHRBEGH SHRBEGL SHRENDH SHRENDL Reserved Reserved DESCRIPTION Quad pixel high data read/write. Most significant nybble = leftmost pixel. Quad pixel low data read/write. Least significant nybble = rightmost pixel. Quad pixel within H line address Quad pixel line address high Quad pixel line address low Loss of sync for channel N, control bits Command register Horizontal offset Vertical offset Shared buffer source channel (0, 2, 4, 6) for even channels, (1, 3, 5, 7) for odd channels Shared buffer beginning line high Shared buffer beginning line low Shared buffer end line high Shared buffer end line low Reserved Reserved
Note: nnn = 000 to 111 for channels 0 to 7, respectively.
Table 3. Channel Block Addressing
ADDRESS 0000xxxx 0001xxxx 0010xxxx 0011xxxx 0100xxxx 0101xxxx 0110xxxx 0111xxxx 1000xxxx 1001xxxx to 1111xxxx CHANNEL 0 1 2 3 4 5 6 7 Multichannel Reserved addresses
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Table 4. Multichannel Block Register Map (Common to All Eight Channels)
ADDRESS 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 TO 10001111 NAME QPH QPL QPHORIZ QPLINEH QPLINEL LOSALL MWRITE CONTROL Reserved DESCRIPTION Quad pixel high data read/write for multiple write Quad pixel low data read/write for multiple write Quad pixel within H line address Quad pixel line address high Quad pixel line address low Loss-of-sync flags for channels 0 through 7 Command register, triggers multiple write(s) Control bits Reserved registers
Table 5. QPLINE Mapping
QPLINE 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 1111 1110 0 1111 1111 1 1111 0010 1 1111 1111 NTSC (VOFFSET = 128) FIELD, LINE Field 1, line 21 Field 2, line 21 Field 1, line 22 Field 2, line 22 Field 1, line 148 Field 2, line 148 Field 2, line 263 -- PAL (VOFFSET = 133) FIELD, LINE Field 1, line 26 Field 2, line 26 Field 1, line 27 Field 2, line 27 Field 1, line 153 Field 2, line 153 -- Field 2, line 276
COMMAND The channel command register allows writing and reading of quad pixel data into external SDRAM memory. The read and write operations are described below: * Writing 0000 0010 to the COMMAND register causes the pixel data in QPH and QPL to be stored into external SDRAM memory. The command register is described below:
BIT7 0 0 0 0
* Writing 0000 0001 to the COMMAND register copies from external SDRAM memory the quad pixels specified by QPHORIZ/QPLINE into QPH/QPL. * Writing 0000 0011 to COMMAND register causes a write followed by a readback to verify the data.
BIT0 0 0 WRITE READ
HOFFSET The channel horizontal offset register defaults at powerup to 128. Values less than 128 shift the OSD image to the left (as viewed on the display), while values greater than 128 shift the OSD image to the right. For example, changing HOFFSET from 128 to 110 shifts the image to the left by approximately 10% of the visible display. Changing HOFFSET from 128 to 156 shifts the image to the right by approximately 10% of the visible display.
The image portion shifted beyond the active video is automatically blanked on any edge. The units of HOFFSET are in quad pixels. Horizontal offset is used to allow flexibility in the video timing for various video sources. Horizontal offset ensures that the first logical OSD pixel is visible on the left-hand edge of the video monitor screen.
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
VOFFSET The channel vertical offset register defaults at power-up to 128. Values less than 128 shift the image up while values greater than 128 shift the OSD image down. For example, changing VOFFSET from 128 to 80 shifts the image up by approximately 10% of the visible display. Changing VOFFSET from 128 to 176 shifts the image down by approximately 10% of the visible display. This register controls the vertical offset of the OSD graphics insertion video. The units of VOFFSET are logical lines. Vertical offset ensures that the first logical OSD graphics line is visible on the video monitor screen. Updates to VOFFSET can take up to two full frame periods to take effect.
SHRSRC Shared memory source channel. A nonzero value in SHRSRC replaces a horizontal band of display with data from another channel. When an SHRSRC channel is selected (nonzero value in the SHRSRC register), the channel's graphics video is generated from the channel's memory, except for the horizontal video lines between (and including) SHRBEGH/L and SHRENDH/L, which instead comes from the memory channel specified by the SHRSRC register (see Applications
Information for more details on how video memory sharing works). Time of actual update, either immediate (asynchronous) or field synchronous, is controlled by the ASYNC flag in the channel command register. Even channels can only be shared with even channels. Odd channels can only be shared with odd channels. Note: If multiple even or odd channels are set to 1, data is taken from the lowest even channel and shared with the higher even channels. This is also true for the odd channels.
The shared memory source channel register is described below:
BIT7 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 BIT0 Ch0
SHRBEGH, SHRBEGL Share begin line HI, share begin line LO. This register pair contains a 9-bit address, which specifies the starting horizontal line to be used from the shared video frame buffer memory. SHRBEG HI contains only 1 bit, which resides in the LSB position (bit 0) of the SHRBEG HI register. The lower 8 bits of the 9-bit address are specified by SHRBEG LO. Valid shared line numbers range from 0 to 483 NTSC (511 PAL). The ASYNC flag in the channel status register controls the time of actual update, either immediate (asynchronous) or video field synchronous. SHRBEGH contains the upper bits of the starting line address and SHRBEGL contains the lower bits of the line starting address. To allow the entire value to be changed at once, the internal value of SHRBEG (which uses both SHRBEGH and SHRBEGL) is not updated until SHRBEGL is written. A write to SHRBEGH alone does not trigger an update of the internal SHRBEG value.
SHRENDH, SHRENDL This register pair, share end line HI, share end line LO, contains a 9-bit address, which specifies the ending horizontal line to be used from the shared video frame buffer memory. SHREND HI contains only 1 bit, which resides in the LSB position (bit 0) of the SHREND HI register. The lower 8 bits of the 9-bit address are specified by SHREND LO. Valid shared line numbers range from 0 to 483 visible NTSC (511 PAL). The ASYNC flag in the channel status register controls the time of actual update, either immediate (asynchronous) or video field synchronous. To allow the entire value to be changed at once, the internal value of SHREND (which uses both SHRENDH and SHRENDL) is not updated until SHRENDL is written. A write to SHRENDH alone does not trigger an update of the internal SHREND value.
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Detailed Description of the Multichannel Block Registers
QPH, QPL Pixel data is read/written 16 bits at a time to the quad pixel registers due to the SDRAM memory organization. The most significant 4 bits (nybble) of QPH represents the leftmost pixel and the least significant 4 bits of QPL represents the rightmost pixel (4 bits per pixel). Table 1 shows pixel data mapping. QPH and QPL for the multichannel block is read/written the same as the individual channel-N register function, except multichannel pixel data is used for multiple write operations to selected channels. QPHORIZ This 8-bit value is the address of the quad pixel within the line specified by QPLINE HI and QPLINE LO. A zero value in QPHORIZ addresses the leftmost displayed quad pixel in the specified line and increasing QPHORIZ addresses indexes towards the right-hand side of the video screen. This register addresses multichannel write operations. Valid values range from zero to 177. Write a 1 in the HINC bit of the multichannel CONTROL register to enable autoincrement of QPHORIZ. QPHORIZ autoincrement saturates at 177. QPLINEH, QPLINEL This 9-bit address specifies the horizontal line of the quad pixel to be accessed (host read or write). QPLINE HI is only 1 bit that resides in the LSB (bit 0) of the QPLINE HI register. The lower 8 bits of the 9-bit address are specified by QPLINE LO. Valid displayed line numbers range from 0 to 483 NTSC (511 PAL). This register is used for addressing for multichannel write operations. Write a 1 in the VINC bit of the channel CONTROL register to enable autoincrement of QPLINE_. QPLINE_ autoincrement saturates at 511.
MAX4455
LOSALL This register is common to all eight channels and reflects the status of sync presence on each of the eight VIDIN_ inputs. If valid composite sync is present at each of the eight VIDIN_ inputs, this register contains all zeros. If any channel loses sync for more than one horizontal line period, a flag is set for that respective
BIT7 Ch7 Ch6 Ch5 Ch4
channel indicating sync loss. Normally, the host processor polls this register periodically and checks for nonzero flag bits, indicating loss of video on any or all channels. This feature detects vandalism, security threats, or simple camera/link failure. The loss of sync register is described below:
BIT0 Ch3 Ch2 Ch1 Ch0
MWRITE Multiple write command register. Trigger multiple write operations to OSD frame buffer memory by writing to MWRITE, specifying which channels should receive data. This is useful in updating graphics common to
BIT7 Ch7 Ch6 Ch5 Ch4
multiple channels (i.e., time of day, etc.). Writing a 1 triggers writes to the desired channel as defined below. This register autoclears itself after a multiple write cycle completes. The multiple write register is described below:
BIT0 Ch3 Ch2 Ch1 Ch0
Control Control bits for the multichannel block register. VINC, when set to 1, enables autoincrement of QPLINEH/L in the multichannel block after each host multichannel
BIT7 0 0 0 VINC
write to OSD memory. HINC, when set to 1, enables autoincrement of QPHORIZ in the multichannel block after each host multichannel write operation to OSD buffer memory. The control register is described below:
BIT0 HINC 0 0 0
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
*OPTIONAL COMPONENTS. USED TO ATTENUATE THE COLOR BURST SIGNAL OF COLOR CAMERAS TO AVOID FALSE TRIGGERING OF THE SYNC DETECTOR IN THE MAX4455. 430* 470pF* VDD
0.1F
VDD MAX4358 VIDEO CROSSPOINT SWITCH OSDKEY_ SWITCH MATRIX
CAMERA VK1 MAX4455 OSD CHANNEL-N PORTION OF MEMORY ALLOCATED TO CHANNEL VIDEO TIMING EXTRACTION AND CONTROL VIDIN_
MEMORY INTERFACE
MICROCONTROLLER
CPU INTERFACE
DIGITAL LINE BUFFERS
4-BIT D/A 75 OSDFILL_ (FAST MUX) CAMERA +OSD
Figure 7. Interfacing MAX4455 with MAX4358 Video Crosspoint Switch
Applications Information
Interfacing to Maxim Video Crosspoint Switches
The MAX4455 interfaces directly to MAX4356/MAX4358 video crosspoint switches with OSD insertion function (Figure 7). The MAX4455 OSDKEY_ and OSDFILL_ outputs connect directly to the OSDKEY_ and OSDFILL_ inputs on the MAX4356/MAX4358 and utilize the internal fast mux in the MAX4356/MAX4358 to implement the OSD insertion. To ensure correct video timing, the MAX4455 VIDIN_ input senses and extracts the video timing directly from the crosspoint switch output.
is low, the OSDFILL_ analog signal on channel IN0 passes through the mux and the OSD information is inserted into the video image. When the OSDKEY_ signal is high, the camera video output passes through the mux and is displayed on the monitor.
Channel Blanking During Video Input Source Switching
Before switching input video sources on a channel with active OSD, set the BLANK bit to 1 in the channel status register to prevent OSDKEY assertion during the video blanking interval. Failure to blank the OSD prior to switching input video sources can cause OSD information to be inserted over the new video input's vertical blanking interval, resulting in a loss of sync on that channel. The MAX4455 timing synchronizes to the video output of the channel, such that switching another asynchronous input video source can cause writing of OSD information over the new video source with unpredictable results (i.e., OSD insertion over the vertical blanking interval). The channel blanking procedure follows: 1) Set BLANK = 1. 2) Switch camera/video source input. 3) Set BLANK = 0.
Interfacing the MAX4455 with a Fast Mux Switch
The MAX4455 interfaces directly to a fast mux switch, as shown in Figure 8. Choose a device with a switch time of less than 30ns, such as the MAX4258, for accurate OSD insertion. The MAX4258 is a single-channel wideband video amplifier with input multiplexing and a channel-tochannel switching time of 20ns. Configure the amplifier using external resistors for a 6dB gain to drive a 75 back-terminated video line. Connect the OSDFILL_ output of the MAX4455 to IN0 of the MAX4258 and connect the video source (camera output) to IN1. Connect the OSDKEY_ output of the MAX4455 to A0, the channel select input of the MAX4258. When the OSDKEY_ signal
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
510 510
+5V FB TO MAX4455 VIDIN_ INPUT
OSDFILL_ (FROM MAX4455) +1 IN0
+1 75
MAX4258
-5V
CAMERA
OUT1 SWITCH MATRIX
IN1
AO OSDKEY_ (FROM MAX4455)
Figure 8. Interfacing MAX4455 with a Fast Mux Switch
The result of writing OSD over the vertical blanking interval is a rolling picture that the display monitor cannot sync to, and the MAX4455 loss-of-sync flag is set for that channel. Reestablish sync by blanking the channel's OSD for at least one full video frame period, allowing the MAX4455's sync timing circuitry to correctly sense the new video source's timing, and reset the LOS flag.
Mitsubishi M2V64S40DTP, Micron MT48LC4M16A2, and Hitachi HM5264165F.
Anti-Aliasing and Flicker
The MAX4455 is a high-resolution graphics system capable of accurately displaying a single pixel line. A line with the height of one pixel, by definition, occurs only on one of the two interlaced fields that make up the standard interlaced video signal. Since the interlaced system has a frame rate of about 60Hz, the field rate is half of this (30Hz). Any object occurring only on one field is displayed at a 30Hz rate, resulting in a flickering image. Any signal displayed at less than a 50Hz rate is perceived to visibly flicker. The slower the display rate is, the higher the perceived flicker. The amount of flicker in a one-pixel-high horizontal line is dependent on the length of the line. The flicker associated with very short lines that are part of another shape are typically very minimal. For example, the flicker of the legs of the letter F is almost imperceptible. At the other extreme, a one-pixel horizontal line that spans the width of a display exhibits flicker that can be very noticeable. The perceived flicker due to thin horizontal lines can be minimized by making the line thicker or by using antialiasing techniques. For the best results, these two
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Optimizing OSDFILL Load Termination and RRSET
The MAX4455 provides standard 100 IRE (0.714V) fullscale OSDFILL_ output levels with RRSET = 11.75k and OSDFILL_ terminated with ROSDFILL_ = 75 to AGND. The MAX4455 OSDFILL_ outputs can drive as high as 1.5V by selecting a lower RRSET value, or increasing the value of ROSDFILL, or a combination of both. OSDFILL output levels higher than 0.714V can have increased distortion and degraded linearity (see the OSDFILL_ Reference Voltage (RSET) section).
SDRAM Memory Selection
The MAX4455 EV kit uses the Micron MT48LC1M16TG7S SDRAM. The MAX4455 has not been tested with, but is designed to operate with the following SDRAMS: Micron MT48LC1M16A1-8 or faster, VIS VG3617161DT-8 or faster, Hyundai HY57V161610D or HY57V161610C,
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Arbitrary Graphics On-Screen Display Video Generator
techniques can be used in conjunction. A thicker line exhibits much less of the flicker effect. Once the line is from five to six lines thick, the additional improvement from thicker lines is negligible. Anti-aliasing is a fairly well-known technique that involves decreasing the severity of the transition of the graphic or font structure. Here, it involves bracketing a horizontal line with two or more other lines that have a relative brightness that is between the brightness level of the line and the background. This is illustrated in Figure 9. The proper application of this technique softens the look of the line, which can be undesirable in some cases. In general, it makes the display easier to read.
MAX4455
Memory Sharing
Memory sharing is a feature that reduces the host processor burden for tasks such as time-stamp update. The MAX4455 supports user-specified starting and ending lines to be shared by any number of channels. In Figure 13, the time stamp is written only to channel 0 on line start through line end. Graphics data stored in lines outside of start and end remain unique for each of the eight video channels (Figure 13). In Figure 13, channel 0's start line number through end line number are duplicated onto channel 2 and channel 4's display. The source of shared data is defined in the SHRSHC register (see the MAX4455 Registed Description section). For example, channel 15 can be programmed to display channel 7's graphics beginning at channel 7 start line #n through end line #m, etc. Sharing is restricted to even channels with even channels and odd channels with odd channels. For example, channels 1, 3, 5, 7 can share lines and channels 0, 2, 4, 6 can share lines in any combination.
Finite Switch Time Effects
The MAX4455 generates the OSDFILL_ and OSDKEY_ signals time coincident with each other within a few nanoseconds. Since the OSDKEY_ signal controls when the external fast mux switch switches from normal camera video to the OSDFILL signal, any finite delay in the response time of this fast mux switch has an effect on the resulting OSD insertion (Figure 10). Due to the finite switching time of the fast mux switch, both the leading and trailing portions of the OSDFILL_ are inserted slightly later in time. The leading edge does not create a visible artifact on the screen since it only shifts the image to the right an amount equal to the switch delay. The trailing edge of the OSDFILL_ can result in a visible artifact because the OSDFILL_ signal has already returned to 0 IRE before the fast mux switch can transition back to the camera video signal. This effect is shown in Figure 11. In a typical NTSC system with a bandwidth of 4.2MHz, the narrowest resolved image is about 120ns wide. If the delay of the fast mux switch is less than half of this, 60ns or less, no visible artifact should be seen on the display. The displayed information can be designed to dramatically minimize the adverse effect of the finite switch time, if desired. For example, virtually all fonts and graphics that are overlayed on normal video need to be outlined for good readability. A very common technique is to use white structures with a black outline border. To compensate for the above finite switch time effect, construct the graphic or font with a thinner trailing edge. When displayed, it looks symmetrical with the trailing edge appearing normal. Figure 12 illustrates this technique.
Power Supplies and Bypassing
The MAX4455 operates from a single 2.7V to 5.5V analog supply and a 3V to 3.6V digital supply. Additional logic supplies for host P interface (VH1) and the OSDKEY_ interface (VK1) allow the MAX4455 to interface with other logic supplies from 2.7V to 5.5V. Bypass each supply pin with a 0.1F capacitor to ground.
Layout Concerns
For best performance, make the OSDFILL_ and OSDKEY_ output traces as short as possible, and place the 75 termination resistor close to the crosspoint switch OSDFILL_ input with the resistor terminated to the solid analog ground plane. The SDRAM interface is the highest speed connection and therefore requires careful layout. Place the SDRAM close to the MAX4455 to minimize trace lengths. The MAX4455 pinout is optimized for memory bus trace routing to the SDRAM without crossing traces. Refer to the MAX4455 EV kit for a proven PC board layout.
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
REGULAR LINE
ANTI-ALIASED LINE IDEAL
Figure 9. Anti-Aliased Line Drawing
70 IRE CAMERA VIDEO 0 IRE 100 IRE OSD FILL 0 IRE
OSD KEY
EFFECT OF FINITE SWITCH DELAY
FAST MUX SWITCH
CAMERA 100 IRE + OSD FILL 70 IRE 0 IRE
OSD FILL CAMERA
Figure 11. Finite Switch Delay Visual Effect
tD tD
tD = SWITCH DELAY
Figure 10. Finite Switch Time Effects
COMPENSATED MEMORY DATA
OSD RESULT
Figure 12. Compensated Graphics Example ______________________________________________________________________________________ 19
Arbitrary Graphics On-Screen Display Video Generator MAX4455
Programming Examples
The MAX4455 EV kit provides a high-level user interface with free-hand drawing, bit-mapped graphics, and text-insertion tools. Listings 1 through 5 show some pseudocode examples based on the MAX4455 EV kit source code for low-level register access, line drawing, RGB-to-gray-scale conversion, and block memory transfer to the OSD.
Listing 1. Constant Definitions
//--------------------------------------------------------------------------// MAX4455 per-channel registers const unsigned __int8 ch_QPH = 0x00; // quad pixel high (msb = left pixel) const unsigned __int8 ch_QPL = 0x01; // quad pixel low (lsb = right pixel) const unsigned __int8 ch_QPHORIZ = 0x02; // quad pixel horizontal address 0..177 const unsigned __int8 ch_QPLINEH = 0x03; // quad pixel line address 0..483 (511 PAL) const unsigned __int8 ch_QPLINEL = 0x04; // low byte of QPLINE const unsigned __int8 ch_STATUS = 0x05; // status { 0 0 0 VINC HINC ASYNC BLANK LOS } const unsigned __int8 ch_STATUS_VINC = 0x10; // auto-increment vertical const unsigned __int8 ch_STATUS_HINC = 0x08; // auto-increment horizontal const unsigned __int8 ch_STATUS_ASYNC = 0x04; // asynchronous write const unsigned __int8 ch_STATUS_BLANK = 0x02; // supress on-screen display const unsigned __int8 ch_STATUS_LOS = 0x01; // (read-only) loss of sync const unsigned __int8 ch_COMMAND = 0x06; // command { 0 0 0 0 0 0 WRITE READ } const unsigned __int8 ch_COMMAND_WRITE = 0x02; const unsigned __int8 ch_COMMAND_READ = 0x01; const unsigned __int8 ch_HOFFSET = 0x07; // horizontal offset (128U = zero offset) const unsigned __int8 ch_VOFFSET = 0x08; // vertical offset (128U = zero offset) const unsigned __int8 ch_SHRSRC = 0x09; // shared buffer source const unsigned __int8 ch_SHRBEGH = 0x0A; // shared buffer beginning line const unsigned __int8 ch_SHRBEGL = 0x0B; // const unsigned __int8 ch_SHRENDH = 0x0C; // shared buffer end line const unsigned __int8 ch_SHRENDL = 0x0D; // // MAX4455 channel register banks const unsigned __int8 CH0_regs = 0x00; // register base for channel 0 registers const unsigned __int8 CH1_regs = 0x10; // register base for channel 1 registers const unsigned __int8 CH2_regs = 0x20; // register base for channel 2 registers const unsigned __int8 CH3_regs = 0x30; // register base for channel 3 registers const unsigned __int8 CH4_regs = 0x40; // register base for channel 4 registers const unsigned __int8 CH5_regs = 0x50; // register base for channel 5 registers const unsigned __int8 CH6_regs = 0x60; // register base for channel 6 registers const unsigned __int8 CH7_regs = 0x70; // register base for channel 7 registers const unsigned __int8 MWRITE_regs = 0x80; // register base for multi-channel write
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Listing 1. Constant Definitions (continued)
// MAX4455 all-channel registers const unsigned __int8 LOSALL = const unsigned __int8 LOSALL_CH7 = const unsigned __int8 LOSALL_CH6 = const unsigned __int8 LOSALL_CH5 = const unsigned __int8 LOSALL_CH4 = const unsigned __int8 LOSALL_CH3 = const unsigned __int8 LOSALL_CH2 = const unsigned __int8 LOSALL_CH1 = const unsigned __int8 LOSALL_CH0 = const unsigned __int8 MWRITE = const unsigned __int8 MWRITE_CH7 = const unsigned __int8 MWRITE_CH6 = const unsigned __int8 MWRITE_CH5 = const unsigned __int8 MWRITE_CH4 = const unsigned __int8 MWRITE_CH3 = const unsigned __int8 MWRITE_CH2 = const unsigned __int8 MWRITE_CH1 = const unsigned __int8 MWRITE_CH0 = const unsigned __int8 CONTROL = const unsigned __int8 CONTROL_VINC const unsigned __int8 CONTROL_HINC 0x85; // loss of sync { CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 } 0x80; 0x40; 0x20; 0x10; 0x08; 0x04; 0x02; 0x01; 0x86; // multiple write { CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 } 0x80; 0x40; 0x20; 0x10; 0x08; 0x04; 0x02; 0x01; 0x87; // auto-increment for MWRITE { 0 0 0 VINC HINC 0 0 0 } = 0x10; = 0x08;
MAX4455
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Listing 2. Low-Level Register Access
//--------------------------------------------------------------------------// Example code: low-level register access. // The MAX4455 Evaluation Software uses a bidirectional parallel port under windows. // Practical applications should use a microprocessor memory or I/O bus. // User-defined subroutine to wait until READY/BUSY signal is READY. // Return false if the BUSY signal seems to be stuck low. extern bool Wait_Until_Ready(void); // User-defined subroutines to read and write the host data bus extern void Set_Data(int value); extern int Get_Data(void); // User-defined subroutine to write the host control lines extern void Set_Control(int value); // Example control bus state values. #define ADDR 0x80 #define DATA 0x00 #define WR_low 0x00 #define WR_high 0x40 #define RD_low 0x00 #define RD_high 0x20 #define CS 0x01 // Control bus state when writing a MAX4455 register address unsigned char ucCtrl8_Addr_Wr = ADDR | WR_low | RD_high | CS; // Control bus state when idle after writing address unsigned char ucCtrl8_Addr_Idle = ADDR | WR_high | RD_high | CS; // Control bus state when writing MAX4455 register data unsigned char ucCtrl8_Data_Wr = DATA | WR_low | RD_high | CS; // Control bus state when reading MAX4455 register data unsigned char ucCtrl8_Data_Rd = ADDR | WR_high | RD_low
| CS;
// Control bus state when idle after reading or writing data unsigned char ucCtrl8_Data_Idle = ADDR | WR_high | RD_high | CS;
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Listing 2. Low-Level Register Access (continued)
bool Try_DUT_Register_Write(const int addr8, const int data8) { if (Wait_Until_Ready() == false) return false; Set_Control(ucCtrl8_Addr_Wr); Set_Data(addr8); Set_Control(ucCtrl8_Addr_Idle); if (Wait_Until_Ready() == false) return false; Set_Control(ucCtrl8_Data_Wr); Set_Data(data8); Set_Control(ucCtrl8_Data_Idle); return true; } bool Try_DUT_Register_Read(const int addr8, int* ptrdata) { int ucdata8; if (Wait_Until_Ready() == false) return false; Set_Control(ucCtrl8_Addr_Wr); Set_Data(addr8); Set_Control(ucCtrl8_Addr_Idle); if (Wait_Until_Ready() == false) return false; Set_Control(ucCtrl8_Data_Rd); ucdata8 = Get_Data(); Set_Control(ucCtrl8_Data_Idle); (*ptrdata) = ucdata8; return true; }
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Listing 3. Horizontal Line Draw
//--------------------------------------------------------------------------//--------------------------------------------------------------------------// Example code: Drawing a horizontal line. // External definitions required for: // Read_Register // Write_Register //--------------------------------------------------------------------------// Drawing primitives for On-Screen Display memory // Draw a line in the OSDEVKIT's display memory. void osd_hline (int ch_base, int xleft, int xright, int y) { // In the STATUS register, set HINC=1 and clear VINC=0 unsigned __int8 status = Read_Register(ch_base | ch_STATUS); status &=~ ch_STATUS_VINC; status |= ch_STATUS_HINC; Write_Register(ch_base | ch_STATUS, status); unsigned char linel = y & 0xff; unsigned char lineh = (y & 0x100) >> 8; Write_Register(ch_base | ch_QPLINEH, lineh); Write_Register(ch_base | ch_QPLINEL, linel); unsigned char horiz = (int) (floor(xleft / 4.0 + 0.5)) & 0xff; Write_Register(ch_base | ch_QPHORIZ, horiz); int width = xright - xleft; width = (int) (floor(width / 4.0 + 0.5)); while(width-- > 0) { // Under Windows, be a good citizen and service the message quque. Application->ProcessMessages(); if (Application->Terminated) break; Write_Register(ch_base | ch_COMMAND, ch_COMMAND_WRITE); } }
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Listing 4. Rectangle Block Copy
//--------------------------------------------------------------------------//--------------------------------------------------------------------------// Example code: Copying a block from host memory to the on-screen display. // External definitions required for: // Read_Register // Write_Register // get_quadpixels (x, y, nybble_3, nybble_2, nybble_1, nybble_0); //--------------------------------------------------------------------------// Copy a rectangular area from PC memory to the On Screen Display memory // Registers affected: ch_STATUS, ch_QPH, ch_QPL, ch_QPLINEH, ch_QPLINEL, ch_QPHORIZ void osd_from_win (int ch_base, TCanvas* canvas, int xleft, int ytop, int xright, int ybottom) { // In the STATUS register, set HINC=1 and clear VINC=0 unsigned __int8 status = Read_Register(ch_base | ch_STATUS); status &=~ ch_STATUS_VINC; status |= ch_STATUS_HINC; Write_Register(ch_base | ch_STATUS, status); // Make sure that xleft and xright are on quad pixel boundaries xleft = (int) (floor(xleft / 4.0 + 0.5)) * 4; xright = (int) (floor(xright / 4.0 + 0.5) + 1) * 4; for (int y = ytop; y <= ybottom; y++) { // Under Windows, be a good citizen and service the message quque. Application->ProcessMessages(); if (Application->Terminated) return; unsigned char linel = y & 0xff; unsigned char lineh = (y & 0x100) >> 8; Write_Register(ch_base | ch_QPLINEH, lineh); Write_Register(ch_base | ch_QPLINEL, linel); unsigned char horiz = (int) (floor(xleft / 4.0 + 0.5)) & 0xff; Write_Register(ch_base | ch_QPHORIZ, horiz); for (int x = xleft; x <= xright; x += 4) { // In the MAX4455 Evaluation Software, // the picture is copied from the host's screen. // A real application would replace win_get_quadpixels with // an application-specific data generating routine. int nybble_3, nybble_2, nybble_1, nybble_0; get_quadpixels (x, y, nybble_3, nybble_2, nybble_1, nybble_0); unsigned __int8 qph = nybble_3 * unsigned __int8 qpl = nybble_1 * Write_Register(ch_base | ch_QPH, Write_Register(ch_base | ch_QPL, 0x10 + nybble_2; 0x10 + nybble_0; qph); qpl);
Write_Register(ch_base | ch_COMMAND, ch_COMMAND_WRITE); } } }
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Listing 5. Converting RGB to 4-Bit Gray Scale
//--------------------------------------------------------------------------//--------------------------------------------------------------------------// Example code: converting RGB values to 4-bit key+luma control value. //--------------------------------------------------------------------------// convert TColor (RGB) to a 4-bit color value for the MAX4455 // // This 4-bit value controls OSDFILL and OSDKEY as follows: // // 0000 transparent // 0001 black // 0010 lighter black // 0111 medium gray // 1110 lightest gray // 1111 white // // The RGB equations are based on Keith Jack's book, // Video Demystified, chapter 3, "Color Spaces", // which is copyright 2001 LLH Technology Publishing. // ISBN: 1-878707-56-6 // URL: http://www.video-demystified.com/ // unsigned __int8 RGB_To_OSDFILL(TColor color) { unsigned __int8 osd_control_value; if (color == clTransparent) { osd_control_value = 0; // transparent } else { // convert TColor into red, green, blue values in the range 0..255 unsigned __int8 red = (color >> 0) & 0xFF; unsigned __int8 green = (color >> 8U) & 0xFFU; unsigned __int8 blue = (color >> 16U) & 0xFFU; const double ar = 0.299, ag = 0.587, ab = 0.114, offset = 0; double luma = ar * red + ag * green + ab * blue + offset; // maximum luma value is 255 unsigned __int8 greyscale_nybble = ((luma * 16.0) / 256) + 0.5; if (greyscale_nybble > 15+1) { greyscale_nybble = 15+1; // white limit } if (greyscale_nybble < 1+1) { greyscale_nybble = 1+1; // black limit } osd_control_value = greyscale_nybble - 1; } return osd_control_value; }
26
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
CHANNEL 0 MEMORY BUFFER CHANNEL 2 MEMORY BUFFER
START LINE NO. 12:30:59 PM END LINE NO. CHANNEL 4 MEMORY BUFFER 12:30:59 PM
START LINE NO. 12:30:59 PM END LINE NO.
Figure 13. Example of OSD Memory Sharing
Chip Information
TRANSISTOR COUNT: 197,669 PROCESS: CMOS
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Pin Configuration
89 OSDFILL1 87 OSDFILL2 91 OSDFILL0 83 OSDFILL4 81 OSDFILL5 85 OSDFILL3 77 OSDFILL7 79 OSDFILL6
TOP VIEW
98 VIDIN4 99 VIDIN3 97 VIDIN5 96 VIDIN6 100 VIDIN2 95 VIDIN7 94 AGND 92 AVDD 93 RSET
88 AVDD
86 AVDD
84 AVDD
82 AVDD
80 AVDD
90 AVDD
78 AVDD
VIDIN1 VIDIN0 VH1 DGND CS WR RD ADDR/DATA AD7
1 2 3 4 5 6 7 8 9
76 AVDD
75 74 73 72 71 70 69 68 67 66 65
DGND XTAL2 XTAL1/SYNC DGND DVDD OSDKEY7 OSDKEY6 OSDKEY5 OSDKEY4 DGND VK1 OSDKEY3 OSDKEY2 OSDKEY1 OSDKEY0 A3 A2 DGND DVDD A1 A0 A10 BA RAS CAS
AD6 10 AD5 11 AD4 12 AD3 13 AD2 14 AD1 15 AD0 16 RDY/BSY 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 DVDD 24 DGND 25
MAX4455
64 63 62 61 60 59 58 57 56 55 54 53 52 51
D15 28
D14 29
D13 30
D12 31
D7 27
D8 37
DQM 38
CLK 39
A9 40
DVDD 41
DGND 42
A8 43
A7 44
A6 45
A5 46
A4 47
WE 48
DVDD 49
TQFP
28
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DGND 50
DVDD 32
DGND 33
D11 34
D10 35
D9 36
D6 26
Arbitrary Graphics On-Screen Display Video Generator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 14x14x1.00L TQPF, EXP. PAD.EPS
MAX4455
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Arbitrary Graphics On-Screen Display Video Generator MAX4455
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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